October 31st 2026, Athens, Greece
Recent advances in AI systems (software and hardware) have resulted in an unprecedented growth in demand for AI-infused computational
models across a very broad range of application domains. Predictably, challenges in efficiency, reliability, security (including privacy),
trustworthiness and safety (of AI systems) have emerged concurrently as major themes of R&D. Closely tied to the challenge of energy
efficiency is the issue of sustainable cost, as evidenced by the recent sensation caused by the emergence of DeepSeek AI. Agile co-design
of hardware and software for AI is a key element of efficiency enhancement and the drive towards sustainable AI compute. To this end, this
tutorial will focus on agile design of secure and resilient AI (SARA) systems.
Our methodology builds on prior work on agile domain-specific system-on-chip (DSSoC) design during the 5-year EPOCHS project led by IBM
(DARPA-sponsored, with Columbia University participating as one of the key university partners). At the core of the EPOCHS project is
ESP, an open-source platform for heterogeneous SoC design from Columbia University. By combining a scalable, modular, tile-based architecture
with a flexible system-level design methodology, ESP simplifies the design of individual accelerators and automates their hardware/software
integration into complete SoCs. This tutorial will begin with a hands-on introduction to ESP. We will detail how ESP was used to successfully
design two complex heterogeneous SoCs during the EPOCHS project and also demonstrate the software stack that runs on our hardware
prototypes. The novel distributed hardware power management architecture will also be covered, detailing the pre-silicon modeling and
design challenges.
In the second part of the tutorial, we will pivot to the SARA application domain, detailing key challenges in “efficient resilience” such as side channel attack mitigation and data security, as well as data integrity or inferential accuracy shortfalls under low power constraints. We will then present our ongoing work to design large systems (e.g. design proposals from IBM or other recent FHE hardware accelerator papers published at top-tier architecture conference) that have support for data-secure AI. This work includes enhancements to ESP to make its NoC-based infrastructure more flexible and performant, which is critical for these complex applications. We will also present the software stack that enables the deployment of SARA workloads across multiple accelerator instances; this includes both privacy-preserving computing, as well as plaintext inference with CNN and Transformer networks. We will wrap up by presenting a vision for future SARA systems-in-package (SiPs) that are composed of multiple chiplets.
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Saturday, October 31st, 2026 (all times are local conference time) |
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|---|---|
| 9:00 - 9:30 AM |
Tutorial Introduction Pradip Bose (IBM) |
| 9:30 - 10:15 AM |
ESP Mini-Tutorial Luca Carloni (Columbia University) |
| 10:15 - 11:00 AM |
Illustrative Use of ESP to Design Efficient CAV SoCs (EPOCHS) and Beyond Luca Carloni (Columbia University) |
| 11:00 - 11:30 AM | Coffee Break |
| 11:30 AM - 12:30 PM |
Introduction to FHE Algorithms and Architectures Charanjit Jutla (IBM) |
| 12:30 - 1:00 PM |
A Brief Survey of Published FHE Hardware Accelerators Yongmo Park (IBM) |
| 1:00 - 2:30 PM | Lunch Break |
| 2:30 - 3:00 PM |
IBM's AI Hardware Accelerator Roadmap Jeff Burns (IBM) |
| 3:00 - 3:30 PM |
Security and Resilience Challenges in AI-Centric Systems Pradip Bose and Naorin Hossain (IBM) |
| 3:30 - 4:15 PM |
IBM's SARA SoC Project: Application-Driven Architecture Definition and Evaluation Pradip Bose and John-David Wellman (IBM) |
| 4:15 - 4:30 PM | Coffee Break |
| 4:30 - 5:15 PM |
HELayers Driven Software Stack for AI/FHE Appliances Eyal Kushnir et al. (IBM Israel Research Laboratory, Haifa) |
| 5:15 - 5:30 PM |
Retrofitting Data Security onto Existing AI Hardware Accelerators Nandhini Chandramoorthy (IBM) |
| 5:30 - 5:45 PM |
AI-Aided Enhancement of Agile SoC Design Methodology Luca Carloni (Columbia University) |
| 5:30 - 5:45 PM |
Quick Recap and Closing Remarks Pradip Bose (IBM) |
| 5:45 PM | End of SARA Tutorial (see you next year!) |
Luca Carloni is professor and chair of Computer Science at Columbia University in the City of New York. He holds a Laurea Degree Summa cum Laude in Electronics Engineering from the University of Bologna, Italy, and the M.S and Ph.D degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley. His research interests include heterogeneous computing, system-on-chip platforms, embedded systems, and open-source hardware. He is an IEEE Fellow.
Joseph Zuckerman is a Computer Science Ph.D candidate at Columbia University, working in the System-Level Design group. His research interests include agile design methodologies, novel architectures, and runtime optimization of heterogeneous systems-on-chip. Joseph currently leads the development of ESP.
Pradip Bose is a Distinguished Research Scientist and manager of Efficient and Resilient Systems at IBM T. J. Watson Research Center. He has over thirty-three years of experience at IBM, and was a member of the pioneering RISC super scalar project at IBM (a pre-cursor to the first RS/6000 system product). He holds a Ph.D. degree from University of Illinois at Urbana-Champaign.
Nandhini Chandramoorthy is a Staff Research Scientist at IBM T. J. Watson Research Center, working in the Dept. of Efficient and Resilient Systems. She holds M.S & Ph.D degrees in EE/CS from Penn State University. Her research interests include: efficient and resilient AI systems, privacy-protected computation and associated modeling methodologies.
SARA will be held in conjunction with the 59th International Symposium on Microarchitecture (MICRO 2026). Refer to the main venue to continue with the registration process.
InterContinental Athenaeum Athens Hotel
Athens, Greece
Check venue page for more information.